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MRF89XA
TX Mode:
3.11.8
ADDITIONAL INFORMATION TO
1.
2.
3.
4.
Program TX start condition and IRQs: Start TX
when FIFO is not empty (IRQ0TXST = 1 ) and
IRQ1 mapped to TXDONE (IRQ1TX = 1 )
Set CMOD = Stand-by mode and enable FIFO
access in Stand-by mode.
Write all payload bytes into FIFO (FRWAXS = 0 ,
Stand-by interrupts can be used if needed).
Go to TX mode. When TX is ready (automati-
cally handled) TX starts (IRQ0TXST = 1 ).
HANDLE PACKET MODE
If the number of bytes filled for transmission is greater
than the actual length of the packet to be transmitted
and IRQ0TXST = 1 , the FIFO is cleared after the
packet has been transmitted. Therefore, the extra
bytes in the FIFO are lost. Otherwise, if IRQ0TXST = 0 ,
the extra bytes are kept in the FIFO. This opens up the
possibility of transmitting more than one packet by fill-
ing the FIFO with multiple packet messages.
5. Wait for TXDONE interrupt (plus one bit period).
6. Go to Sleep mode.
RX Mode:
It is not possible to receive multiple packets. After a
packet has been received and filled in the FIFO all its
contents needs to be read (that is, the FIFO must be
empty for a new packet reception to be initiated).
1.
2.
3.
4.
5.
6.
Program RX/Stand-by interrupts: IRQ0 mapped
to FIFOEMPTY (IRQ0RXS = 10 ) and IRQ1
mapped to FIFO Threshold (IRQ1RXS = 00 ).
Configure FIFO Threshold to an appropriate
value (for example, to detect packet end, if its
length is known).
Go to RX mode by setting the CMOD register.
FIFO threshold interrupt, when the FIFO is full
with received contents. So you have to enable
IRQ1 to “CRCOK” interrupt.
Wait for CRCOK interrupt.
Go to Stand-by mode.
Read payload byte from FIFO until FIFOEMPTY
goes low. (FRWAXS = 1 ).
Go to Sleep mode.
The PLREADY interrupt goes high when the last pay-
load byte is available in the FIFO and remains high until
all its data are read. Similar behavior is applicable to
ARDSMATCH and CRCOK interrupts.
The CRC result is available in the STSCRCEN bit
immediately as the CRCOK and PLREADY interrupt
sources are triggered. In RX mode, the STSCRCEN bit
is cleared when the complete payload has been read
from the FIFO. If the payload is read in Stand-by mode,
the STSCRCEN bit is cleared when the user goes back
to RX mode and a new Sync word is detected.
The FIFOFM and FIFOFSC bits have no meaning in
Packet mode and should be set to their default values
only.
3.11.9 PACKET MODE REGISTERS
The registers associated with Packet mode are:
?
GCONREG ( Register 2-1 )
?
DMODREG ( Register 2-2 )
?
FDEVREG ( Register 2-3 )
?
BRSREG ( Register 2-4 )
?
FLTHREG ( Register 2-5 )
?
FIFOCREG ( Register 2-6 )
?
FTXRXIREG ( Register 2-14 )
?
FTPRIREG ( Register 2-15 )
?
RSTHIREG ( Register 2-16 )
?
FILCREG ( Register 2-17 )
?
PFCREG ( Register 2-18 )
?
SYNCREG ( Register 2-19 )
?
RSTSREG ( Register 2-21 )
?
OOKCREG ( Register 2-22 )
?
SYNCV31REG ( Register 2-23 )
?
SYNCV23REG ( Register 2-24 )
?
SYNCV15REG ( Register 2-25 )
?
SYNCV07REG ( Register 2-26 )
?
PLOADREG ( Register 2-29 )
?
NADDSREG ( Register 2-30 )
?
PKTCREG ( Register 2-31 )
?
FCRCREG ( Register 2-32 )
? 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 89
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